Output: 2 cycles high, 1 cycle low → 33% duty, frequency = clk/3. Fractional division (e.g., divide by 2.5) is essential for generating arbitrary frequencies from a fixed crystal. It is achieved by periodically swallowing clock edges using a phase accumulator.
module prog_divider #(parameter WIDTH=16) ( input clk, rst_n, input [WIDTH-1:0] divisor, // N value output reg clk_out ); reg [WIDTH-1:0] count; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin count <= 0; clk_out <= 0; end else begin if (count == divisor - 1) begin count <= 0; clk_out <= ~clk_out; end else begin count <= count + 1; end end end endmodule verilog frequency divider
module div_by_3 ( input clk, rst_n, output reg clk_out ); reg [1:0] count; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin count <= 0; clk_out <= 0; end else begin if (count == 2) begin // 0,1,2 -> 3 cycles count <= 0; clk_out <= ~clk_out; end else begin count <= count + 1; end end end endmodule Output: 2 cycles high, 1 cycle low →
Caveat: The divisor value must be ≥ 2 and stable during operation. For very high input frequencies (e.g., 500 MHz in an ASIC), counter propagation delay may limit performance. Use synchronous prescalers with low-bit ripple counters or Johnson counters. input [WIDTH-1:0] divisor